1. Field of the Invention
The invention relates in general to a method of evaluating semiconductor circuit yield, and more particularly to a statistical method of evaluating gate oxide layer yield.
2. Description of the Related Art
In the fabrication process of semiconductor devices, wafer acceptance testing (WAT) is often carried out to check gate oxide layer failure distribution of a transistor on a wafer. The method is provided by forming a number of test keys around a particular die on the wafer to perform testing. These test keys are formed on scribe lines between neighboring dies, and are electrically connected to external components, devices, or testing devices via bonding pads. A module of the test keys is selected for testing different device characteristics such as threshold voltage V.sub.TH and saturation current I.sub.DSAT, etc. Whether the test keys fails or not can be detected by measuring a current signal while applying a voltage to the test keys. The yield of the module is N/M, where the module comprises M test keys and there are N keys that have not failed after testing.
FIG. 1 is a top view showing a conventional wafer structure. In FIG. 1, a number of rectangular dies 12 are formed on a wafer 10. Scribe lines 14 are formed with a set of vertical lines perpendicularly intersecting with a set of horizontal lines. The dies 12 are isolated from each other by these scribe lines 14. While forming a transistor on a particular die 12, similar structures are formed on the scribe lines 14 for testing. Therefore, a part of the gate oxide layer of the transistor on the particular die 12 also covers the scribe lines 14. While performing WAT, the part of the gate oxide layer on the scribe lines 14 is electrically connected to an external detector through a bonding pad 16. The WAT result reflects the quality or characteristics of devices formed on each die 12. Therefore, yield of transistors formed on a wafer can be obtained.
As shown in FIG. 2, a gate oxide layer with a large area Ab can be divided into several small areas As. The failure distribution of the large area oxide Ab and the failure distribution of the small area oxide As are in a multiplication relationship. Assume that there are 10 Ab and each Ab is divided into 100 As. As a total, all the large areas Ab are divided into 1000 times the small areas As. If one of the small areas As fails, the large areas Ab also fails. According to the result described above, the failure percentage of Ab will be in general larger that the failure percentage of As. Furthermore, if the failure percentage of a gate oxide layer is X, the yield of the gate oxide layer is (1-X). A formula relates the yield and the area size will be presented later.
Before manufacturing new semiconductor devices, it is necessary to determine the quality of gate oxide layers of the semiconductor devices. A curve of failure distribution versus charge density is obtained to represent the quality of the gate oxide layers. A varying testing voltage is applied on test keys to obtain a charge density of the test keys. When the applied voltages increase, the charge density also increases. With an increase in charge density, the test keys fail one after another.
Many test keys are tested to obtain the curve of failure distribution versus charge density. If a percentage of failure distribution is 0.01%, 10000 test keys must be tested. This methodology requires a lot of testing time and a large sample size to accumulate data to obtain the gate oxide layer yield. The result is that a WAT operation is difficult to perform.